Hi Matrix Community,
I’ve been playing with matrix voice and recorded tones at different frequencies. With original FPGA code on matrix voice, I get around 160Hz frequency offset. I’ve looked at the FPGA code to figure out this problem. Here is my finding.
In “matrixvoicefpga/voice_core/system.v” there is a parameter “PDM_FREQ_HZ” which is equal 3_000_000. When I change this value, the frequency offset changes.
FPGA code:
parameter PDM_FREQ_HZ = 3_000_000 , /* this frequency must be multiple of 16000, 22000, 44000, 48000 Hz /*
My questions:
 Should this parameter be a multiple of the values above as it mentioned? If yes, why it’s not in the code?
 Is 22000 and 44000 correct? If this is related to audio rate, should we consider 22050 and 44100?
I appreciate if anyone can help on this.
Thanks.
@mehrdadh,
The PDM_FREQ_HZ variable is set to 3 MHz as that is close to the fastest PDM rate supported by the microphones on the MATRIX Voice (see max input clock frequency on datasheet).
We wanted the PDM sampling frequency to be as high as possible to gain resolution.
To answer your questions:

The comment is a bit misleading. Typically, the oversampled PDM frequency is about, if not more, than 64 times greater than the baseband sampling frequency. 48 kHz x 64 ~= 3 MHz and so that number provides sufficient resolution for the lower frequencies as well.

The values in the comment represent sampling frequencies and should be 22050 and 44100. We will update it. Thanks!
Regarding the frequency offset. Given that the PDM frequency is 3 MHz, the decimation ratio varies depending on what baseband sampling rate you desire.
The numbers here in this array are in the order {target sampling rate, decimation ratio, gain}. What the sampling rate actually ends up being depends on the decimation ratio and since the numbers need to be integers, there’s a margin of error.
For example, for the 8 kHz target sampling rate, the actual sampling rate comes out to 3 000 000/374 ~= 8021 Hz, and so the sampling rate will be 21 Hz off. This is likely why you are experiencing a frequency offset.
Best,
Samreen
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Thanks for you response.
My other question is about the FPGA max frequency. In the datasheet the max frequency depends on the speed grade. I appreciate if you can provide information about the FPGA max frequency support and its speed grade.
Thanks
Hi @mehrdadh,
The speed grade of our FPGA is 2.
Regarding the max frequency, our hardware engineers advise logging it from the FPGA compilation output since it is determined during the synthesis process.
You can try
make clean
make > log
Xilinx ISE also has a CLI command called speedprint that may help you.
Best,
Samreen