Microphone DSP Opened, 100% Open Source Software!


Dear MATRIX Community,

After much deliberation, we are happy to announce that we have decided to open up all of the FPGA source code, including the microphone digital signal processing algorithms, to our community. We are now a 100% open-source software platform! Below are the links to the full FPGA Code.

Full MATRIX Creator FPGA Code
Full MATRIX Voice FPGA Code

We believe that this crucial step will further enable you to leverage the full potential of the MATRIX platform by presenting you with the opportunity to modify and enhance the DSP for your project or product.

As we continue to develop the MATRIX platform, we are constantly looking for how we can improve, and best serve our community. We appreciate your continued support and we look forward to seeing what you create. Happy building!


Matrix voice GPIO
[Solved] Microphone Array FPGA source code
[SOLVED] I2S speaker with Matrix Voice

This is awesome, nothing to hide, nothing to worry about


Beyond my skills, but great news anyway :slight_smile:

1 Like

I simply use the Voice board for the scientific work of studying the DOA and deconvolution in the rooms. Opening fсpga code is a good step forward. I regard it so that you finally asked for help from the community in order to make a product with a great design better.


I haven’t looked at the code yet, but if it isn’t already there, I strongly recommend having a simple bus to support “plugins” in a way that relieves us of having to hack the existing FPGA source to make room for our additions. The mics need it for sure, but all I/O should also benefit.


Would you please commit a .vcd file for a testbench run on the current code? That would help us not only validate our own builds, but also serve as a learning point.


what do you mean with a simple bus? Do you want to configure hardware behavior /options through the bus?

From my little understanding of the code the Zwave implementation is using such a mechanic on the wishbone bus to configure a gpio. so maybe this could be used to configure other stuff or to enabled disable features.


the MAKEFILE contain targets (postsim / iversim) that seems to generate a .vcd file and then starts gtkwave using this file.

i tested both targets with iversim (icarus verilog) installed but both failed maybe these are outdated targets, or need more treatment.

after some minor Makefile modifications, mostly pointing to the correct ISE WebPack installation folder it has used the creator_TB.v (testbench) to generate an vcd file. here the results in gtkwave:


I’ve worked with other FPGA projects that built, but had latent errors. Having “blessed” .vcd files lets a simple comparison help isolate such issues. Of course, getting a 100% match is the goal of the first build, not just being free of obvious errors.

More than once, parts of the testbench itself were left out…


A “simple” bus is often inherent in projects intended to be easy to modify, expand and evolve, where it ties together not only the project’s own components, but makes it easy to add more components both in parallel and in series just by managing the bus, rather than detangling stateful register-based interfaces.

Such busses can be as simple as I2C (bit-serial), or go up to say, AMBA. I’ve used ones that were serdes-based (for FPGAs having lots of internal serdes transceivers), but that’s less common (though still simple).

I’ve never designed one myself, but no matter how complex the implementation (and some seem very complex), it’s a minimal and elegant interface that makes them “simple”.


they are currently using a wishbone bus on the FPGA, i don’t know if this is some sort of bus you mean:


Really need the schematic to make full sense of this.